In Built-In Self-Test (BIST), test patterns are generated and applied to the circuit-under-test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers (LFSR). Conventional LFSRs normally requires more number of test patterns for test...

The purpose of FPGA on-line checking is to detect faults that occurs in-field. Depending on whether circuit logic is affected permanently, in-field faults can be categorized into temporal and permanent faults. Temporal faults may come from single-event-upset, ground bounce, power supply noise or crosstalk. Moreover, permanent faults are due to silicon aging, electro-migration and wire/device bu...

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.

The objective of the BIST is to reduce power dissipation without affecting the fault coverage. Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generati...

The increased circuit density in today’s integrated circuits demands for efficient and low cost testing as compared to the testing of logic with external test equipment. The Built-In Self Test (BIST) architecture provides the self-testing of logic circuit but is not at the positive extreme in delivering deterministic and limited test vectors and storage and compression of output test responses....

A sine waveform signal generator for the on chip testing of mixed-signal circuits for speech processing is present. The idea behind is to attenuate the higher frequencies in a periodic triangular waveform. The hardware implementation is discussed. And the simulation results validate our proposal. This generator can be employed for both the digital BIST and the analog/mixed-signal BIST applicati...

The advantages of Built-In Self-Test (BIST) are well known, and for embedded memories BIST is already the preferred test method. However, for random logic BIST is less often employed. This is mainly due to the following two reasons: On the one hand, deterministic patterns might be necessary to achieve reasonable fault coverage, yet they are expensive in built-in tests. On the other hand, the di...

Built-In-Self-Test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means to perform in-theeld diagnostics. This paper discusses a Mixed AnalogDigital BIST (MADBIST) for a Signal-to-Noise-Ratio test of an Analog-to-Digital Converter. The MADBIST strategy for the SNR test of the A/D Converter...

In this paper, a new BIST(Built-In Self-Test) structure for efficient test of embedded RAMs is proposed. In proposed embedded memory BIST(EMBIST) architecture, various algorithms are allowed to be executed, and just one controller can test more than one embedded memories. And, the proposed EMBIST has efficient structure that requires smaller hardware overhead. The experimental result demonstrat...

An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of different cores. In this paper, we overview BIST method...