Over two decades, a problem of location dependent has been focused for improving the communication Bandwidth-Power Efficiency of homogeneous networks. The efficiencies of communication links are weakened by the Hidden Terminal Problem.  Thus we propose a Fine – Tune Strategy for analyzing the On-Off communication region. We were observed that the proposed technique had been able to track and mo...

With CMOS technology being scaled to ever smaller dimensions to achieve higher performance and integration levels, power dissipation has become a major concern in modern VLSI designs. Sub-threshold circuits have gained a lot of importance due to ultra low-power consumption. The paper reviews the sub-threshold circuit design. Various body-biasing schemes and logic families for performance enhanc...

This paper investigates the power of Probabilistic Büchi Automata (PBA) when the threshold probability of acceptance is non-extremal, i.e., is a value strictly between 0 and 1. Many practical randomized algorithms are designed to work under non-extremal threshold probabilities and thus it is important to study power of PBAs for such cases. The paper presents a number of surprising expressivenes...

In this paper a technique is presented which improves the noise immunity of TSPC circuit. This technique is compared with other existing techniques. Analysis is carried out both for super and sub-threshold regions of operation. Investigations consider different performance criteria viz. n ooise immunity curve, power consumption, delay, average noise threshold energy (ANTE), PANTE and DANTE. The...

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal—oxide—semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can re...

This paper presents a novel current mode four quadrant multiplier. A pair of sub threshold translinear loops and current conveyors are the basic building blocks in realization scheme. The proposed multiplier features simplicity, low power dissipation. The salient features of this approach are; it‟s single ended inputs; since it uses sub threshold region of operation, this make the design intere...

In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low p...

This paper analyzes the difference between two techniques of power saving circuit design. As the number of transistors increases power consumption and the need for more power efficient products increases there is greater motivation to design circuits to fulfill these expectations. We will give a comparison between these two technologies using an adder as the basic circuit. We will compare the p...

CMOS image sensor (CIS) VLSI architecture based on time to threshold pulse width modulation an era of processor which habituated on the successful representation of low power and high speed applications. This paper deals with current mode logic based PWM architecture which dealt with various analysis of power, delay and power delay product.The pixel circuit will perform in many switched devices...

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipation than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power superthreshold computing scheme is proposed to reduce power...