High-level area-time estimation is an essential step to facilitate rapid design exploration for FPGA implementations. Existing works in high-level area-time estimation usually ignore the physical effects of the design after place and route, which have a notable impact on the maximum achievable speed of the design. In this paper, we propose a framework to rapidly estimate the area-time measures ...

Modern processors rely on exception handling mechanisms to detect errors and to implement various features such as virtual memory. However, these mechanisms are typically hardwareintensive because of the need to buffer partially-completed instructions to implement precise exceptions and enforce in-order instruction commit, often leading to issues with performance and energy efficiency. The situ...

Embedded systems have pervaded all walks of our life. With the increasing importance of mobile embedded systems and flexible applications, considerable progress in research has been made for power management. Power constraints are increasingly becoming the critical component of the design specifications of these systems. It helps in pre-determining the suitable hardware architecture for the tar...

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communicat...

As modular weapon systems allow cost-effective upgrades of a vessel’s war-fighting capability, the degradation of the difficult-to-upgrade structure of the vessel may soon become one of the key drivers of vessel retirement and lifecycle maintenance costing. Existing structural design approaches are reviewed, along with recent developments in this field. It is argued that recent research has pro...