The paper outlines the increasing popularity of Hardware Description Languages (HDL), the advantages of VHDL and the reasons it gained an important position in engineering education. Special attention is paid to some difficulties that students meet when VHDL is first introduced to them. The good practices and recommendations are considered and an approach to help the students to overcome these ...

This paper presents a study on the VHDL implementation of a class of binary irregular structured LDPC codes (IS-LDPC) applied to 100 Gbps optical networks. A comparison between two iterative decoding algorithms for irregular structured LDPC codes, sum-product based on loglikelihood ratio and min-sum, is used to define the best choice for implementation. The performances of IS-LDPC codes are eva...

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulat...

In this paper we address the problem of software generation from a Hardware Description Language (HDL). In particular, we examine the issues involved in translating VHDL into C or C++ for use in system simulation and cosynthesis. Because of the concurrency supported by VHDL, and a notion of timing behavior, care must be taken to ensure behavioral correctness of the generated software. The issue...

Designers are increasingly using VHDL for high-level modeling. However, their task is hindered by the lack of object-oriented and genericity features in the language. Experience in programming languages shows that these features significantly aid management of complexity in large designs and promote re-use of modules. SUAVE extends VHDL by adapting several object-oriented and genericity feature...

Considering the importance of real time filtering, a comparison was done between two prominent window techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique (Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness and other properties of the digital filter. Further a hardware descriptiv...