مداخل يعسوت رامعم ميمصت " ةجاحلا بسح ةددعتم طئاسو " ABSTRACT in this paper we develop a Vhdlbased scalable architecture of a multimedia on demand server model. Te three server subsystems are:the control subsystem, the communication subsystem and the storage subsystem are modeled. The communication subsystem is designed as an interconnection network with meshed-pipe structure and delivers packe...

In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; th...

Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today’s wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 ms. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the require...

A new algorithm is presented to control an MPPT (Maximum Power Point Tracker) through an FPGA (Field Programmable Gate Array). The photovoltaic module was assumed to be connected to a generic load by means of a DC/DC converter controlled through the MPPT. Under these conditions, and for given temperature and solar radiation values, the power supplied by the module was successfully controlled by...

This paper presents the architecture and modeling of RSA public key encryption/decryption systems. It supports multiple key sizes like 128 bits, 256 bits, 512 bits. Therefore it can easily be fit into the different systems requiring different levels of security. In this paper simple shift and add algorithm is used to implement the blocks. It makes the processing time faster and used comparative...

Abstract—This paper analyzes the experimental investigation of indirect field oriented control of Field Programmable Gate Array (FPGA) based five-phase induction motor drive. A detailed d-q modeling and Space Vector Pulse Width Modulation (SVPWM) technique of 5-phase drive is elaborated in this paper. In the proposed work, the prototype model of 1 hp 5-phase Voltage Source Inverter (VSI) fed dr...

The state of the art in hardware design is the use of hardware description languages such as VHDL (Very High Speed Integrated Circuit Hardware Description Language). The designs given by VHDL programs are reened up to the point where the physical realization of the new circuit or board can be synthesized automatically. The designs are tested by simulating them and comparing their output to that...

The automatic diagnosis of breast cancer (BC) is an important, real-world medical problem. This paper proposes a design of automated detection, segmentation, and classification of breast cancer nuclei using a fuzzy logic. The first step is based on segmentation using an active contour for cell tracking and isolating of the nucleus in the cytological image. Then from this nucleus, have been extr...

In efforts to overcome the complexity of the syntax and the lack of formal semantics in conventional hardware description languages (most notably Verilog and VHDL), a number of approaches based on functional languages have been proposed. The merits of functional languages as hardware description languages can be attributed to the fact that basic building blocks for hardware circuits are equival...

Knowledge of hardware description languages is an important element in the educational background of both undergraduate and graduate electrical and computer engineering students. However, the manner in which they are exposed to hardware description languages should differ because of the different level of maturity of the student populations. Graduate students are mature intellectually and thus ...