It is shown that any left module A over a ring R can be written as the intersection of a downward directed system of injective submodules of an injective module; equivalently, as an inverse limit of one-to-one homomorphisms of injectives. If R is left Noetherian, A can also be written as the inverse limit of a system of surjective homomorphisms of injectives. Some questions are raised. The flat...

In this paper we talk about mixed architectures of a H.264/AVC video decoder. Here software part of decoder was implemented in NIOS II processor on a FPGA prototyping board (Stratix III). Software and hardware architectures was proposed to increase the decoder output performance. Based upon the time execution parameters, data dependency constraints, the decoder partitioning is applied. Here the...

approved: The computation of th GF(p) or GF(2), is one o applications. In this work, w the design of efficient hard inverse. We suggest a new c inverse algorithm to calcula a fast hardware algorithm proposed designs have the h on constrained areas and sti calculations, the module w module operates, can be se upper limit on the operand operands and internal resul infinite-precision Montgome We a...

This paper has completed the hardware design of STM32F103 system circuit, infrared code learning module, human body infrared sensor module, indoor temperature and humidity sensor module, completes the software design of learning air conditioning remote control code, indoor temperature and humidity sensor module, also completes the energy-saving controller hardware and software debugging. Finall...

We use graceful labellings of paths to give a new way of constructing terraces for cyclic groups. These terraces are then used to find cyclic solutions to the three table Oberwolfach problem, OP(r, r, s), where two of the tables have equal size. In particular we show that, for every odd r ≥ 3 and even r with 4 ≤ r ≤ 16, there is a number Nr such that there is a cyclic solution to OP(r, r, s) wh...

This paper presents two architectures for 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first consists of transform module, RAM module and address sequencer. The transform module, which takes uniform and regular structure with local communication, offers many advantages, e.g. simple control flow, full hardware-utilization and low-power. The second architecture features parall...

A high-speed real-time decoder for t-errorcorrecting binary Bose-Chaudhuri-Hocquenghem (BCH) codes based on a modified step-by-step decoding algorithm is presented. The average operation cycles for decoding each received word is just equal to the block length of the codeword. The decoder is constructed by three modules: the syndrome module, the comparison module, and the error corrector. Since ...