Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it possible to exploit high on-chip memory bandwidth by widening on-chip bus and on-chip DRAM array. In addition, from energy consumption point of view, the integration brings a significant improvement by decreasing the number of off-chip accesses. For merged DRAM/logic LSIs having on-chip cache me...

Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framew...

We present Mlcached, multi-level DRAM-NAND keyvalue cache, that is designed to enable independent resource provisioning of DRAM and NAND flash memory by completely decoupling each caching layers. Mlcached utilizes DRAM for L1 cache and our new KVcache device for L2 cache. The index-integrated FTL is implemented in the KV-cache device to eliminate any inmemory indexes that prohibit the independe...

[email protected] [email protected] Abstract— This Paper Deals With the Design and Analysis of 3T1D DRAM Cell to develop Process Variation Architectures using Cadence Tool. With continued technology scaling, process variations will be especially Detrimental to Threetransistor One Diode Dynamic memory structures (3T1D DRAM). A Memory architecture using three-transistor, onediode DRAM...

The main memory system is a critical component of modern computer systems. Dynamic Random Access Memory (DRAM) based memory designs dominate the industry due to mature device technology and low cost. These designs, however, face several challenges moving forward. These challenges arise due to legacy DRAM device design choices, advances in Central Processing Unit (CPU) design, and the demand for...

There is an increasing interest in developing Phase Change Memory (PCM) based main memory systems. In order to retain the latency benefits of DRAM, such systems typically have a small DRAM buffer as a part of the main memory. However, for these systems to be widely adopted, limitations of PCM such as low write endurance and expensive writes need to be addressed. In this paper, we propose PCMawa...

For more than four decades, the simple structure of the dynamic RAM (DRAM) cell and continuous improvement in lithography and dry-etching technology has made DRAM grow exponentially in a large-scale integration and has decreased the minimum feature size in memory chips. In the field of testing, more appropriate test algorithms are required to protect DRAM cell data.In this paper an Interleaving...

Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate pertask DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, such as per-task energy-aware task scheduling and energy-aware billing in datacenters. In particular, the contributions of this paper are (i) an ideal per-task energy metering ...

This paper proposes a software-controllable variable linesize (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected t...