Abstract: In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digi...

The dependence of the shift of an optical bistability hysteresis curve on the nonlinear phase shift induced by a controlling light is observed in a four-level atomic system of 87 Rb inside an optical ring cavity. In the process the intensity of the coupling beam keeps constant and the atomic system is operated at near conditions of coherent population trapping due to atomic coherence. The refra...

The latches are simple circuits with feedback from the digital electrical engineering. We have included in our work the C element of Muller, the RS latch, the clocked RS latch, the D latch and also circuits containing two interconnected latches: the edge triggered RS flip-flop, the D flip-flop, the JK flip-flop, the T flip-flop. The purpose of this study is to model with equations the previous ...

The register element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of register ...

-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered...

-In many digital Very Large Scale Integration design, clock system is one of the most power consumption component. It consumes 30% to 60% of the total system power. As we are in need to reduce the power consumption on portable digital circuit because power budget is severely limited on portable digital circuit. To achieve this requirement, a clock system employing two techniques such as Dual Ed...