An approach and its implementation in 0.18 μm CMOS process of the multichannel ASIC for capacitive (up to 30 pF) sensors are described in the paper. The main design aim was to study an analog data-driven architecture. The design was done for an analog derandomizing function of the 128 to 16 structure. That means that the ASIC structure should provide a parallel front-end readout of 128 input an...

An Arithmetic Logic Unit (ALU) is the heart of every central processing unit (CPU) which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using appli...

This paper proposed a system-on-chip (SOC) architecture for speech recognition which is speaker dependent. The feature extraction bases on LPC (linear predictive coefficient)-cepstrum coefficients, and template matching employs Hidden Markov Models (HMM). It does not aim to offer a sophisticated solution but rather a high speed solution. This SOC architecture includes an ASIC of LPC-cepstrum an...

A possibility to overcome the problem of organizing a diploma–thesis at a distance university with focus on practice in the design of Application Specific Integrated Circuits (ASICs) is presented with the aid of an example. A student of electrical engineering designed a fast arithmetical unit for use in a digital filter with a VHDL software package (ALLIANCE [see laboratory 1994]) freely distri...

This essay reviews those basic facts about (univariate) B-splines that are of interest in CAGD. The intent is to give a self-contained and complete development of the material in as simple and direct a way as possible. For this reason, the B-splines are defined via the recurrence relations, thus avoiding the discussion of divided differences which the traditional definition of a B-spline as a d...

PARISROC is a complete read out chip in AMS SiGe 0.35μm technology for photomultipliers array. It is made to allow triggerless acquisition for next generation neutrino experiments. The ASIC integrates 16 independent channels with variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter.

This paper presents a codesign methodology and environment for both hardware and software modules design of telecommunication systems. We describe how High Level Synthesis (HLS) tools like GAUT and SYNDEX can be efficiently used for rapid prototyping of heterogeneous architecture based on DSP TMS320C40 and ASIC. As an illustration, we present a mixed implementation of the GMDF alpha algorithm, ...

As a good trade-off between CPU and ASIC, FPGA is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques, such as (i) smooth stair-step flow, (ii)...