Our concern is the design of provably correct asynchronous circuits. In such circuits there may occur hazards, due to the delay of signals along wires and components. Informally, a hazard is a time interval during which the output of a circuit, or circuit component, is wrong. Hazards are hardly ever de ned formally in the literature. For a synchronous circuit designer this might be no problem a...

Architecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations have been applied to create a power efficient architecture of an FFT. This architecture has been implemented in asynchronous circuit technology that achieves significant power reduction over other FFT architectures. Multirate signal processing concepts are applied to the F...

We investigate asynchronous circuit veri cation using Dill s trace theory as well as Milner s CCS as mechanized by the Concur rency Workbench Trace theory is a formalism speci cally designed for asynchronous circuit speci cation and veri cation CCS is a gen eral purpose calculus of communicating systems that is being recently applied for hardware speci cation and veri cation Although both forma...

In this paper we present a novel design approach that combines the advantages of on-chip switched networks (OCSNs) and the globally asynchronous, locally synchronous (GALS) design methodology using the mechanism of asynchronous FIFO buffers. Our proposed two GALS OCSN models were synthesized with 0.25μm Chip Express structured ASIC library. Comparative simulations were performed for these two p...

The performance of linear multiuser receivers in terms of the Signal-to-Interference Ratio (SIR) achieved by the users has been analyzed in a synchronous CDMA system under random spreading sequences. In this paper, we extend these results to a symbol-asynchronous system and characterize the SIR for linear receivers | the Matched Filter receiver, the MMSE receiver and the Decorrelator. We rst an...

Two digital systems working in different clock domains require a protocol to communicate with each other in order to ensure validity of the data being shared between the two systems. Such systems are said to be asynchronous, and the protocol used for communication is said to synchronize the two systems. Asynchronous design techniques are not as widely used as synchronous design techniques are. ...

The complexity of digital design and time-to-market have arose many challenges in synchronous design methodology; the need for high frequency and low skew clock distribution with its profound effect on final circuits take a lot of time and implementation cost. Asynchronous design methodology by eliminating global clock and replacing synchronization with handshaking is not yet much promising for...

We compare two 16 bit adders based on the Manchester Carry Chain (MCC) circuit topology using the TSMC .25 µm process technology. The first circuit is a synchronous 16 bit adder based on an optimized 4-bit MCC where the carry out of each of the 4-bit MCCs are ripple carried into the next MCC block through an edge sensitive D-Flip Flop. The second circuit is an asynchronous adder, which uses the...

Asynchronous design has been an active area of research since at least the mid 1950's, but has yet to achieve widespread use. We examine the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies. These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive cir...

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental ...