In BIST architecture the ATPG is the one of important consideration .the performance also the depends on the appropriate ATPG generation .in our paper we propose the novel method of multiple single input change (MSIC) test patterns that are intended for the scan chain. In order to develop any method we need to consider the area and power aspects for the advanced VLSI designs, and also able to p...

Abstract — A diagnostic automatic test pattern generation (DATPG) system is constructed by adding new algorithmic capabilities to conventional ATPG and fault simulation programs. The system generates tests to distinguish between fault pairs through different output responses. Given a fault pair, by modifying circuit netlist a new single fault is modeled and targeted for detection by a conventio...

We study the problem of fault propagation, which is a very important and time consuming task performed by an ATPG tool, and develop a generic framework that supports generation of propagation functions per circuit line for both logic and timing faults. The proposed methodology is an alternative to the traditional function-based ATPG techniques for logic errors (such as stuck-at faults), but can...

Identifying legal and illegal states significantly reduces computational complexity of ATPG. A unified framework for identification of the legal and illegal states is presented. Most known methods for identification of the legal and illegal states are interpretable within this framework. New theorems and the resulting procedures for identifying exact collection of legal or illegal states of a c...

Unbounded model checking methods based on Boolean satisfiability (SAT) solvers are proving to be a viable alternative to BDD-based model checking. These methods include, for example, interpolation based and sequential ATPG-based approaches. In this paper, we explore the implications of using abstraction refinement in conjunction with interpolation-based model checking. Based on experiments usin...

Low Power Design is a critical concern and metric for today's complex designs. During scan based manufacturing test, power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues w...

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic pattern generation (ATPG) tools that lead to zero-defect is still an open problem. It challenging detect all stuck-at faults reach 100% In parallel, the hardware security community has been actively involved develo...

Currently, Very Large Scale Integrated (VLSI) circuits and the resulting digital systems are widely used in almost all areas of human’s life. To ensure the validity of these systems, error-free VLSI circuits are becoming more and more important. With the increasing complexity of VLSI circuits, the cost for the test on VLSI circuits has risen dramatically. So it is necessary to reduce the cost o...