When TCP is carried over 3G links, overbuffering and buffer overflow at the RLC layer degrades its performance. AQM techniques at the RLC buffer can bring noticeable enhancements to TCP performance without introducing changes in 3G specifications. We show that the optimum parameter setting of AQM algorithms in RLC buffers is strongly related to the radio bearer rate, which can be changed dynami...

This work presents an analysis of the buffer features of an access router, especially the size, the impact on delay and the packet loss rate. In particular, we study how these features can affect the Quality of Service (QoS) of multimedia applications when generating traffic bursts in local networks. First, we show how in a typical SME (Small and Medium Enterprise) network in which several mult...

This paper presents a comprehensive survey of existing techniques for interconnect optimizationduring the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various d...

A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps: generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullatornorator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullator...

This paper describes the operation of three types of charge pump circuits. Power efficiency theory of charge pumps is discussed. A method of estimating the output ripple of a charge pump from the size of the capacitors used is described. A new charge pump circuit that uses two cascoded buffer transistors to improve the area efficiency is proposed.

The Best Paper award went to “Control Flow Integrity for COTS Binaries,” by Mingwei Zhang and R. Sekar (Stony Brook Univer­ sity). The Best Student Paper award was presented to “Securing Computer Hardware Using 3D Integrated Circuit (IC) Technol­ ogy and Split Manufacturing for Obfuscation,” by Frank Imeson, Ariq Emtenan, Siddharth Garg, and Mahesh V. Tripunitara (University of Waterloo). Final...

Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors and two duty cycle control buffers a low cost frequency doubler circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input clock signal with an unpredictable duty cycle is inputted to a rising (or falling) edge detector. The edge detector converts the ...

The source follower circuit is used as a voltage buffer and level shifter. It is more flexible level shifter as the dc value of voltage level can be adjusted by changing aspect ratio of MOSFETs. It is desired to have low output resistance for such applications. Source follower can give minimum output resistance 1/(gm+gmb) with load resistance and channel resistance tending to infinity. The supe...

This paper proposes an active capacitive sensing circuit for fingerprint sensors, which includes a pixel level charge-sharing and charge pump to replace an ADC. This paper also proposes the operating algorithm for 16-level gray scale image. The active capacitive technology is more flexible and can be adjusted to adapt to a wide range of different skin types and environments. The proposed novel ...

This paper reports the effects of the seed layers prepared by spin-coating and dip-coating methods on the morphology and density of ZnO nanowire arrays, thus on the performance of ZnO nanowire-based dye-sensitized solar cells (DSSCs). The nanowire films with the thick ZnO buffer layer (*0.8–1 lm thick) can improve the open circuit voltage of the DSSCs through suppressing carrier recombination, ...