Parallel processing has recently become an extremely attractive and cost effective way of achieving orders of magnitude performance improvements in VLSI CAD applications. In this paper, we propose parallel algorithms to speed up the VLSI circuit extraction task. Given a VLSI layout as input, the problem of circuit extraction consists of determining the circuit connectivity and estimating the va...

In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both the cut and the maximum subdomain degree are simultaneously minimized. This type of partitionings are critical for existing and emerging applications in VLSI CAD as they allow to both minimize and evenly distribute the i...

Binary Decision Diagrams (BDDs) are frequently used in many applications in VLSI CAD. However, they are very sensitive to the variable ordering and their size often becomes infeasible. Recently, a new approach for BDD minimization based on Linear Transformations (LTs), i.e. a special type of spectral techniques, has been proposed. We present an Evolutionary Algorithm (EA) to find an LT for whic...

Even the more or less “canonical”, lower-level architecture of information systems needs to be revisited from time to time. Notions like persistence and transactions belong traditionally to the area of database management systems. There are, however, many applications, such as CAD, VLSI design or simulation, which need persistence and could take advantage of transactions, but require especially...

Binary Decision Diagrams (BDDs) are frequently used in many applications in VLSI CAD. However, they are very sensitive to the variable ordering and their size often becomes infeasible. Recently, a new approach for BDD minimization based on Linear Transformations (LTs), i.e. a special type of spectral techniques, has been proposed. We present an Evolutionary Algorithm (EA) to find an LT for whic...

Optimization of huge sequential circuits has become unmanageable in CAD of VLSI due to enormous time and memory requirements. In this paper, we report a parallel algorithm for the state assignment problem for nite state machines. Our algorithm has three sig-niicant contributions: It is an asynchronous parallel algorithm portable across diierent MIMD machines. Time and memory requirements reduce...

The MIT approach to 3-D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: a) Structural integrity of the Cu-Cu bond, b) CuCu contact electrical characteristics, and c) Process flow efficien...

An important organization for built-in self-test of VLSI circuits uses complete or psuedorandom test input generators followed by output data reduction. Two compression techniques which have been used are polynomial division (signature) and ones counting (syndrome). The simultaneous use of both of these approaches in parallel is investigated. Analytic and enumerative results indicate that the n...

Move-based iterative improvement partitioning methods such as the Fiduccia-Mattheyses (FM) algorithm 3] and Krishnamurthy's Look-Ahead (LA) algorithm 4] are widely used in VLSI CAD applications largely due to their time eeciency and ease of implementation. This class of algorithms is of the \local improvement" type. They generate relatively high quality results for small and medium size circuit...

In the past the major concerns of the VLSI designer were area speed and cost power consideration was typically of secondary importance In recent years how ever this has begun to change and increasingly power is being given comparable weight to other design considerations Several factors have contributed to this trend including the remarkable success and growth of the class of battery powered pe...