As technology continues to scale and decrease in size, the reliability of transistors is becoming an ever increasing problem. Previous second order effects are becoming more pronounced, and other effects, reliability effects, as we shall see, are changing the operation of devices and can even cease to operate properly. The purpose of this project is to investigate device reliability from a hier...

Fundamentals of Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Discrete Solid-State Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.39 Integrated-Circuit Logic Functions . . . . . . . . . . . . . . . . . . . . . ....

Redesign of traditional relays with microcontroller-based relays can be used to achieve a higher level of reliability. In this study, the results of redesign and prototyping of a synchrocheck relay using an 8952 microcontroller with improved reliability is discussed. These relays are usually used for paralleling two load-generation islands, or for closing an open loop in an electric power syste...

Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/ decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitanc...

ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As With dc clamp voltages will also very high. Effort invested in addition to transient surges esd. Circuit protection circuits are limited applying esd used. Te circuit board it to both, accidental short durat...

The FPGA overlay architectures have been mainly proposed to improve design productivity, circuit portability and system debugging. In this paper, we address the use of overlay architectures for building fault tolerant SRAM-based FPGA systems and discuss the main features and design challenges of a reliability-aware overlay architecture. Keywords— FPGAs; Overlay architectures; Reliability; Fault...

Deep submicron technology introduces strong linkages between process, design, and reliability. Papers in this session talk about the effect of process defects on chip reliability estimation, measurement of circuit delay variations due to process variability, and future trends in power supply distribution as a result of interconnect scaling.

Fast and accurate reliability estimation of integrated circuits is an open problem. Introducing the emerging nano devices such as FinFET and Stacked Silicon nanowires makes this problem even more challenging because of higher lithography fluctuation. We discuss several previous efforts for reliable circuit design and propose a methodology for accurate reliability estimation of novel transistors.