This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technolog...

Quantum dot Cellular Automata (QCA) is an emerging digital logic representation techniques and one of the possible alternatives to Complementary Metal–Oxide–Semiconductor (CMOS) technology. It satisfies attractive circuit components of smaller size and low power dissipation of new circuit design technologies. Quantum dots are nano architecture and it works based on columbic interaction between ...

Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary...

To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, sum...

Dynamic pass-transistor logic (PTL), which combines pass-transistor logic with dynamic logic, is proposed for high-performance VLSI circuit design. The dynamic PTL holds the merits of fast evaluation characteristics as dynamic logic. Moreover, because a pre-charged scheme solves the weak logic ‘high’ problem of a static PTL, an additional level restoration circuit is not needed. An 8-bit multip...

An asynchronous circuit, or self-timed circuit, is a sequential digital logic circuit which is not enabled by a global clock signal. Instead of that, they often use signals that indicate completion of operations and instructions, specified by handshaking or simple data transfer protocols. This type is contrasted with a synchronous logic circuit where changes to the output signal values are trig...

In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDNcapacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Ref...

Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It o...

in this paper Gate diffusion input (GDI) technique of Low-power digital circuit design is described and verified in 0.18μm CMOS process. This technique permits reducing power consumption, propagation delay, and area of digital circuits of logic design. Performance comparison with traditional CMOS and pass-transistor logic design techniques is presented. These methods are compared with respect t...

The performance and the power consumption of single-electron transistor (SET) technology-based ultra-energy-efficient signal processing circuits are compared based on the SPICE model including non-ideal effects of the experimental data for the first time. In terms of ultra-energy-efficient logic circuits, the binary decision diagram (BDD) logic circuit is the most promising with a dissipated po...