This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software. And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and lo...

In this paper a new method for the design of a linear phase distributed amplifier in 180nm CMOS technology is presented. The method is based on analogy between transversal filters and distributed amplifiers topologies. In the proposed method the linearity of the phase at frequency range of 0-50 GHz is obtained by using proper weighting factors for each gain stage in cascaded amplifier topology....

This paper presented a new structure for the CMOS power amplifiers as more effective trend to amplify radio frequency (RF) signals compared polar PA's by using envelope removal and restoration (EER) technique. Polar PA offers high-efficiency RF-modulated linear signal amplification. However, these need high uniformity between amplitude phase of modulated signals. The last translates promptly in...

This paper presents a novel stereo enhancement structure for the surround stereo class-D audio amplifier. The principle of this stereo enhancement scheme has been analyzed. It shows that the amplifier with this proposed circuit have a better live effect than the traditional class-D audio amplifiers. In this circuit, the input audio signal from one channel can be amplified in the two channels at...

In this paper two dimensional wave propagation is used for power combining in drain nodes of a distributed amplifier (DA). The proposed two dimensional DA uses an electrical funnel to add the currents of drain nodes. The proposed structure is modified due to gate lines considerations. Total gain improvement is achieved by engineering the characteristic impedance of gate lines and also make appr...

This paper describes the design of a current mode instrumentation amplifier using second generation current conveyor(CCII). The current mode approach offers several advantages such as high speed, better noise performance and lower power consumption as compared to conventional voltage mode approach. The design is implemented in standard 65 nm CMOS technology. Simulation is done in cadence enviro...

In this paper presents a optimization of linearity of low noise amplifier by using post linearization techniques. in this technique we have used diode connected mosfet as IMD sinker also used interstage matching for gain enhancement and reducing the effect of nonlinearity in common gate stage of cascode amplifier, this has done by using UMC .18um CMOS Technology in cadence tool. We got gain 14d...

A 1.8V, 2.4 GHz CMOS low noise amplifier (LNA) is proposed to be used in front end receiver of Wireless LAN (WLAN) and Industrial Scientific and Medicine (ISM) band. The circuit is simulated in tsmc 180nm V 3.2. The optimization for the width of the CMOS is done taking into consideration parameters viz. noise figure (NF), Power consumption, gain, stability and linearity. The matching of input c...

This paper describes a 60-GHz differential power amplifier (PA) designed in a 120-GHz fT 90nm CMOS technology. It consists of three identical differential cascode stages with inter-stage matching implemented by wide-gap coplanar waveguide (CPW) structures and M6M5 plate capacitors. A double-stub network realized by CPWs provides more design freedom for the input matching. Load-pull simulation g...