We present a new sequential normal basis multiplier over GF (2). The gate complexity of our multiplier is significantly reduced from that of Agnew et al. and is comparable to that of Reyhani-Masoleh and Hasan, which is the lowest complexity normal basis multiplier of the same kinds. On the other hand, the critical path delay of our multiplier is same to that of Agnew et al. Therefore it is supp...

Although recursive filters are not possible to pipeline at the algorithmic level, it is possible to introduce logic level pipelining and thereby increase the maximal sample rate. This is because the critical path gets shorter so that the circuitry can be clocked faster. However, the latency of the operations increases with increased pipelining. It is of interest to find the optimal degree of pi...

A new parallel-in-parallel-out bit-level pipelined multi-plier is presented to perform multiplication in GF(2 m). The existing designs use m 2 identical cells each having 7 latches and have a system latency of 3m. We start with the Dependence Graph (DG) of the algorithm and pipleine it to achieve a critical path equal to the delay of a 2-input AND and XOR gate. The critical path in the proposed...

This paper presents a method for optimizing software testing efficiency by identifying the most critical path clusters in a program. We do this by developing variable length Genetic Algorithms that optimize and select the software path clusters which are weighted in accordance with the criticality of the path. Exhaustive software testing is rarely possible because it becomes intractable for eve...

In this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This uncertainty increase forces to add more safety margins to the clock period which produces a circuit performance downgrade. We evaluate three self-adaptive clock systems: free running ring oscillator, infinite impulse response filter controlled ...

We present a technique for redundancy elimination in multiplierless linear systems, such that the critical path of the computations is not increased. To the best of our knowledge this is the only method that combines common subexpression elimination and delay optimization in one single step. We assume that all the constant multiplications are decomposed into additions/subtractions and shift ope...

Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from timing models. Performance verification in the...

Clustered voltage scaling is a power reducing method which does not affect the overall system performance. The main idea is to run gates on a non-critical path by a low-voltage supply. Since low-voltage gates are not able to drive high-voltage gates, level-converters are needed. In order to reduce the number of level-converters, which may cancel out the power savings, they are arranged in a clu...

Different types of software testing techniques and methods have been projected for taking care of these issues. Use of evolutionary algorithms for usual test generation has been an area of interest for many researchers. Genetic Algorithm (GA) is one such type of evolutionary algorithms. In this research paper, we current a study of Genetic Algorithm approach for addressing the different issues ...

The register element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of register ...