The performance of a code tracking loop for a spread spectrum signal can be severely deteriorated in the presence of an interference signal. The interference signal is modeled as a signal with the same code but with a different delay and carrier frequency. The variance of the tracking delay error is derived in terms of loop bandwidth, chip duration, the interference and signal power and bandpas...

A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchro...

The paper studies the dynamics of a conventional positive going zero crossing type digital phase locked loop (ZC1-DPLL) taking non-ideal responses of the loop constituent blocks into account. The finite width of the sampling pulses and the finite propagation delay of the loop subsystems are properly modeled mathematically and the system dynamics is found to change because of their inf luence co...

Coupled phase-locked loops (CPLLs) are introduced as novel circuits for phased-array antennas. Successful implementation relies on characterizing the synchronization behavior of CPLL circuits over a broad range of circuit parameters. Considering inherent time delay in the phase-locked loop demonstrates the degradation in the pull-in and hold-in ranges, as well as circuit instabilities, suggesti...

In a coherent RAKE receiver the complex channel coee-cient estimate can be used to attain the phase coherency in DLL and the eeect of data modulation can be removed via decision feedback. The resulting algorithms are called quasi-coherent delay-locked loops (QCDLL). The performance of four variations for QCDLLs based on lead-lag phase-locked loops has been analyzed by computer simulations. All ...

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations...