System-on-a-chip (SOC) requires integration of analog circuits and digital circuits on a single silicon chip to decrease cost, power dissipation, volume and radiant noise from the data bus on the printed circuit board (PCB). For these mixed-signal intergrated circuits, the standard digital CMOS technology is the best choice in view of cost, power dissipation and implementation convenience. The ...

A new realization of non-recursive digital filters using operation on ternary delta modulated signal is proposed. Direct operation on ternary delta modulated signal will be derived mathematically and a hardware implementation of ternary arithmetic operation will be shown. The primary advantage of the ternary scheme is the simplicity of the hardware and reduction in connections and interconnecti...

This paper describes an H.263 video codec implementation based on a low power consumption general purpose DSP. Fast algorithms, such as a fast motion estimation algorithm and a low complexity noise reduction filter, are proposed to implement the video codec on a single DSP chip maintaining sufficient picture quality. By using a 50MIPS, 100mW DSP, the developed codec encodes and decodes 7.5 QCIF...

With the continuing trends to reduce the chip size and integrates multichip solution into a single chip solution it is important to limit the silicon area required to implement parallel FIR digital filter in VLSI implementation. The Need for high performance and low power digital signal processing is getting increased. Finite Impulse Response (FIR) filters are one of the most widely used fundam...

genomic signal processing is a relatively new field in bioinformatics, in which signal processing algorithms and methods are used to study functional structures in the dna. an appropriate mapping of the dna sequence into one or more numerical sequences enables the use of many digital signal processing tools in the analysis of different genomic sequences. also, a novel influenza a (h1n1) virus o...

This paper presents a design method of on-chip patch antenna integration in a standard CMOS technology without post processing. A 60 GHz on-chip patch antenna is designed utilizing the top metal layer and an intermediate metal layer as the patch and ground plane, respectively. Interference between the patch and digital baseband circuits located beneath the ground plane is analyzed. The 60 GHz o...