In this paper, a 10-bit 0.5V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The e®ect of the latch o®set voltage is reduced by pr...

An all-digital PWM-based delta-sigma (ΔΣ) ADC is proposed. This system takes advantages of the duration of a pulse, rather than voltage or current, as the analog operand used in its closed-loop operation. Unlike VCO-based ADCs, this ADC as a linear input sampling stage with adequate uncalibrated performance. Furthermore, the architecture allows inherently matched multi-bit quantizer/DAC blocks ...

Two methods of computer-controlling an electronic instrument are described. One method employs a computer having as few as two digital-to-analog converters. A second method is shown which can be used if a 16line digital output is available. Features of either method include low cost, high accuracy and stability, low noise and ease of installation. (Submitted to Review of Scientific Instruments)...

Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. Their conversion consists of two stages: Sampling, which maps a continuous-time signal into discrete-time, and quantization, i.e., representing the continuous-amplitude quantities finite number bits. ADCs typically implement generic uniform mappings that are ignorant task for is acquired, can cost...

Asymmetric monotonic switching scheme is proposed for a low power successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed switching procedure consumes no energy from reference voltage for the first 3 MSB (most significant bit) conversion using unequal initial DAC setting and asymmetric binary search algorithm. After 3 MSB conversions, DAC switching utilizes a c...

This paper study the high-level modelling and design of delta-sigma ( ) noise shapers for audio Digital-to-Analog Converter (DAC) so as to eliminate the in-band Signal-to-NoiseRatio (SNR) degradation that accompany one channel mismatch in audio signal. The converter combines a cascaded digital signal interpolation, a noise-shaping single loop delta-sigma modulator with a 5-bit quantizer resolut...

Digital phase reconstruction of directly detected minimum (MP) optical signals using the Kramers-Kronig (KK) algorithm has recently drawn attention because its low hardware complexity. Only a single photodiode is required to detect intensity signal and KK relations are used retrieve information. To make sure by MP, carrier tone needs be inserted. In this work, we digitally add at transmitter, o...

This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce area as well as power dissipation. The current cells of conventional binary weighted architecture require larger size of transistors for MSBs. In this paper, same sized current cell transistors for MSBs as that of LSBs and a current mirror circuit is used between the load and MSBs to provide necessar...