This report describe the implementation of system-level communication on a programmable processor. First, the issues are introduced using the example of communication software on a Motorola DSP. Then, the problem is generalized and defined for the general case of system-level communication on a programmable processor.

This paper describes a new highly accurate fast selfcontained sonar sensor. Transmission and echo analysis are performed at repetition rates exceeding 27 Hz for ranges to 5.4 metres. The sensor contains low noise variable gain preamplifiers, two 1 MHz 12 bit ADC receivers and a DSP echo processor. Optimal arrival time estimation is performed by the DSP using matched filtering of echoes with sho...

The number and variety of products that include some form of digital signal processing has grown dramatically over the last five years. DSP has become a key component in many consumer, communications, medical, and industrial products. These products use a variety of hardware approaches to implement DSP, ranging from the use of off-the-shelf microprocessors to field-programmable gate arrays (FPG...

The first step in implementing digital signal processor (DSP) applications is to test the functional operation of algorithm. Once we are convinced that it fully fulfills required task, second step, implementation, can follow. In vast majority cases, this done a high-level C / ++ language. We not yet optimizing at stage development. If code works completely flawlessly and runs right speed, no fu...

The topic of this thesis is about soft-errors in digital systems. Different aspects of soft-errors have been addressed here, including an accurate simulation model to emulate soft-errors in a gate-level net list, a simulation framework to study the impact of soft-errors in a VHDL design and an efficient architecture to minimize the impact of soft-errors in a DSP processor. The first two chapter...

An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 μW at sub-1V. The DSP consumes only 10 μW at ...

In this paper, we use a digital signal processor (DSP) to implement a real-time H.263+ codec. We use fast algorithms to reduce the codec computational complexity. Furthermore, the C programs are modified to take advantages of the DSP architecture and its C compiler features to reduce the on-chip memory and to increase the processing speed. In addition, a simple but effective ratecontrol algorit...

Digital Signal Processor (DSP) is an emerging technology that offers great opportunities for the development of future wireless communications systems. In this paper, we demonstrate an implementation of real time adaptive beamforming for cdma2000 reverse link using TI C6701 DSP. We consider that the DSP executes least-mean-square (LMS) algorithm for the beamformer weight vector computation. The...

This paper discusses recently introduced strategies in implementing DSP systems using residue replication; in particular we highlight current work underway in the VLSI Research Group, at the University of Windsor, in the area of constructing high throughput DSP systems on silicon. The paper first briefly reviews the theory and mapping techniques, associated with general residue and residue repl...