To reduce power utilization and area are some of the most important criteria for the fabrication of Digital Signal Processing and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. In most of the multiplication, the multiplier is an energyhungry component. To improve energy efficiency of multipliers, the choice of multiplier is very important. Her...

New VLSI circuit architectures for addition and multiplication modulo (2 1) and (2 + 1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are imp...

This paper describes the comparison of VLSI architectures on the basis of Speed, Area and Power of different type of Adders like Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder and 32-bit pipelined Booth Wallace MAC Unit with Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder is designed in which the multiplication is done usi...

An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always i...

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices ofthe phasemode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This ...

the impulse response can be either finite or infinite. The methods for designing and implementing these two filter classes differ considerably. Finite impulse response (FIR) filters are digital filters whose response to unit impulse (unit sample function) is finite in duration. This paper presents the design of low power FIR filter and area efficient parallel linear phase FIR digital filter. Lo...

To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructi...

New VLSI circuit architectures for addition and multiplication modulo (2n 1) and (2n + 1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are i...

This report presents power consumption results of 24-bit hybrid TCS (Tree Carry Select) adders using HEAT tool. Fast binary adder architectures which can be implemented using multiplexers have been proposed in 1]. This binary adders are carried out using fast redundant-to-binary (RB) converter. Two types of RB converters based on tree-type and carry-select were designed. In this report, the low...

This paper presents a comparison of two possible approaches for the efficient implementation of a scalable Montgomery Modular Multiplication (MM) coprocessor on modern Field Programmable Logic Devices (FPLDs). The first implementation uses data path based on traditionally used redundant carry-save adders, the second one exploits standard carry-propagate adder with fast carry chain logic not yet...