The relationship of permanent magnetic material characteristic parameters was analyzed, and a simulation method of a permanent magnet synchronous motor (PMSM) rotor demagnetization fault was put forward. Based on this, a simulation model of the PMSM under partial demagnetization and uniform demagnetization fault were established, and different degrees demagnetization fault was simulated. Relati...

1. Introduction The integrated circuit (IC) design has been pushed to hardware description language (HDL) description and high-level synthesis (HLS) techniques. The IC testing is also going to the high-level one. For the high-level testing, like gate level one, it needs a circuit model at high level such that,-The model is easy to be converted and extended from the HDL descriptions.-The model s...

Currently, in most fault simulators physical defects have to be modeled as stuck-at faults in networks of primitive gates such as AND, NAND etc. Especially for complex gates this modeling technique is rather inexact. In this paper, a fault simulation approach supporting a more powerful and variable fault model is presented. Speciication of faults is done in a cell oriented manner. To achieve ma...

Three programs are described here which have been used for integrated-circuit yield modeling at the IBM facility in Essex Junction, Vermont. The first program generates negative binomial distributions which are used to represent the frequency distribution of the number of faults per chip. Calculations with the generalized combination function A ! B in APL are limited to simulations of up to 99 ...

A number of efforts have been recently devoted to fault modeling, fault simulation and test generation for asynchronous circuits (Shi and Makris 2004). Simulation based approach for testing gate delay faults in asynchronous sequential circuits was proposed by Sur-Kolay et al (2000). Shi and Makris (2006) have proposed a test method for path delay faults based on a design for test strategy. In s...

Real defects (e.g., resistive stuck at or bridging faults) in the very large-scale integration (VLSI) circuits cause intermediate voltages which cannot be modeled as ideal shorts. In this paper, we first show that the traditional zero-resistance model is not sufficient for fault simulation. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simula...

This paper addresses the problem of fault collapsing in asynchronous circuits. We investigate different transistor-level implementations of some basic elements that are used in delay-insensitive asynchronous circuit designs, and analyze them in the presence of single stuckat faults. From this analysis, we conclude that all internal stuck-at faults which are detectable by Boolean testing, can be...

The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SE...