The work here is directed at examining a model predictive control (MPC) implementation that takes advantage of recent advances in the availability of high performance computing platforms at modest cost. The focus here is on the potential for developing custom architecture solutions on field programmable gate array (FPGA) platforms. This is illustrated by demonstrating the solution of a disturba...

This paper presents the QRS complex detection design suitable for implementation in Field Programmable Gate Array (FPGA). It employs the simplest version of Integer Wavelet Transform for signal decomposition and techniques of zero crossing and double tresholding for extraction of R peaks which makes it suitable for application in real-time and cost effective personal healthcare assistance devic...

This paper presents experiences obtained while using a compiler that translates designs written in a parallel programming language into a form suitable for controlling a Field Programmable Gate Array. Although the initial motivation for the project was to develop tools which would assist the implementation of a distributed multi-microprocessor architecture, results have shown that the technique...

In this work we are describing hardware implementation of Kohonen SelfOrganizing Map. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA (Field-Programmable Gate Array). In this article we are describing basic neurocomputer unit structure as well as linkage of these elements ...

Redundancy is a critical component to the design of fault tolerant systems; both hardware and software. This paper explores the possibilities of using evolutionary techniques to first produce a processing system that will perform a required function, and then consider its applicability for producing useful redundancy that can be made use of in the presence of faults, ie is it fault tolerant? Re...

This paper presents the design and implementation of a low-pass, high-pass and a hand-pass Finite Impulse Response (FIR) Filter using SPARTAN-6 Field Programmable Gate Array (FPGA) device. The filter performance is tested using Filter Design and Analysis (FDA) and FIR tools from Mathworks. The FDA Tool is used to define the filter order and coefficients, and the FIR tool is used for Simulink si...

In this paper we present a novel RAM-based field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog ...

This paper presents a new structure for fast GPS receivers. The suggested GPS acquisition scheme leverages a systolic-based array structure of regular and simple locally-connected processing-elements (PEs). The new GPS system is simulated and its complexity is evaluated for a real-time implementation on a field programmable gate array (FPGA). The proposed systolicbased acquisition system promis...

This paper introduces a new field programmable gate array (FPGA) based stochastic low-density parity-check (LDPC) decoding process, to implement fully parallel LDPCdecoders. The proposed technique is designed to optimize the FPGA logic utilisation and to decrease the decoding latency. In order to reduce the complexity, the variable node (VN) output saturated-counter is removed and each VN inter...