In this paper, we present DeFer—a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a nonslicing floorplan by compacting a slicing floorplan. To find a good slicing floorplan, instead of searching through numerous slicing trees by simulated annealing as in traditional approaches, DeFer considers only one single slicing tree. However, we gener...

Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorpla...

print layout, paste-up, floorplanning, genetic algorithm, self-organising documents, BICAS The increasing quantity of data held by organizations about individuals, and the recent development of digital press capable of one-off printing at a quality rivalling offset machines, have created a demand for a method to automatically generate page layouts. The present solutions to this are either to us...

High-performance design flows for FPGAs often rely on module generators to implement fast sub-circuits. However, the very flexibility of current generator systems makes their automatic use by synthesis and floorplanning steps difficult. We present a common model to express generator capabilities and design characteristics to client tools. Examples show how an active query/reply scheme supports ...

The task of 3D physical design is to map a circuit from a netlist (structural) representation into a geometric (physical) representation according to a specific 3D IC technology with multiple active device layers. This paper discusses the recent progress made on the major steps in 3D physical design, including 3D floorplanning, 3D placement, 3D routing and thermal through-silicon via (TS via) p...

Traditionally the oorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the oorplan also a ects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a oorplan. The goal of this paper is to study the two seemingly disjoint ob...

Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show th...

Most of existing floorplanning algorithms evaluate the target area after packing all of the blocks, but random perturbation will make the target area larger or less unpredictably. In this paper, a unified non-slicing area prejudged transitive closure graph (AP-TCG) algorithm is proposed, which can estimate the target area before packing. AP-TCG can indicate whether the perturbation is beneficia...