This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing as...

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a stu...

Design and simulation of conventional CMOS full adder using 45nm technology at specified node has been presented here. This research work shows comparison about post layout simulations of designed low power CMOS full adder. It also explains about performance analysis of optimized low power CMOS full adder at different loads. This design has achieved 63. 11nW active power consumption with propag...

A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dualbit adder design is evaluated and compared vis-à-vis the conventional full add...

Reversible logic has extensive applications in quantum computing, it is a unconventional form of computing where the computational process is reversible, i.e., time-invertible. The main motivation behind the study of this technology is aimed at implementing reversible computing where they offer what is predicted to be the only potential way to improve the energy efficiency of computers beyond v...

The main objectives is to compare the existing full adders circuits and there performances and to design a Low Power Full Adder having improved result as compared to existing full adders. The various full adders are described namely BBL-PT (branch based logic and pass transistor logic based), conventional CMOS full adder and hybrid full adder. Finally comparisons between the various full adders...

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a highspeed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure ...