Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an asynchronous interconnect. Such a scheme can be used for point-to-point communication in a globally asynchronous locally synchronous (GALS) system, a possible methodology for managing the predicted increase in clock do...

In this paper we describe an implementation of a 2dimensional DCT processor and shows that the GALS (Globally Asynchronous Locally Synchronous) approach is highly suitable for implementation of such processors. Primarily it increases the design efficiency by using the divide-and-conquer approach.

It has been suggested that rheumatological disorders are underdiagnosed in patients with medical problems and that this might be rectified by incorporating a standard brief screening examination as part of the routine assessment of all patients admitted to hospital with medical conditions. Therefore the GALS screening examination was used to assess the prevalence of rheumatic disease in 100 pat...

behavioural simulation

The research reported in this dissertation is motivated by two trends in the system-on-chip (SoC) design industry. First, due to the incessant technology scaling, the interconnect delays are getting larger compared to gate delays, leading to multi-cycle delays in communication between functional blocks on the chip, which makes implementing a synchronous global clock difficult, and power consumi...

To study the ground motion level associated with historical earthquakes located in Southern Spain, we have chosen a scenario placed in the Poniente Almeriense (Southeast Spain). In this zone, some relevant historical earthquakes have occurred, such as those of 1522, 1804 and 1910. In particular, the earthquakes of 1804 and 1910 the estimated and calculated magnitudes are of M = 6.3. Those earth...

We propose a mathematical framework to deal with the composition of heterogeneous reactive systems. Our theory allows to establish theorems, from which design techniques can be derived. We illustrate this by two cases: the deployment of synchronous designs over GALS architectures, and the deployment of synchronous designs over the so-called Loosely Time-Triggered Architectures.

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In this paper we discuss some aspects of designing low power asynchronous wrappers for use in GALS based communication systems. We propose a general method for designing asynchronous wrappers for use in asynchronous multiport-to-multiport communication channels with low swing busses and variable power supply voltages.