Available online 17 August 2008 LaLuO3 thin films have bee

Articles you may be interested in Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors Appl. Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors Appl. Effects of gate bias on hot-carrier reliability in drain extended metal-oxide-semiconductor transistors Appl. D...

Continual evolution of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-65 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided metal gate (FUSI) has been proven to be a promising solution. FUSI metal gate can significant...

AlN/GaN single heterojunction MOS-HEMTs grown by molecular beam epitaxy have been fabricated utilising HfO2 high-K dielectrics deposited by atomic layer deposition. Typical DC transfer characteristics of 1.3 mm gate length devices show a maximum drain current of 950 mA/mm and a transconductance of 210 mS/mm with gate currents of 5 mA/mm in pinch-off. Unity gain cutoff frequencies, ft and fmax, ...

Articles you may be interested in O 3-based atomic layer deposition of hexagonal La 2 O 3 films on Si(100) and Ge(100) substrates Atomic layer deposition of La x Zr 1 − x O 2 − δ (x = 0.25) high-k dielectrics for advanced gate stacks Appl. Suppressed growth of unstable low-k Ge O x interlayer in Ge metal-oxide-semiconductor capacitor with high-k gate dielectric by annealing in water vapor Appl....

High permittivity (k) gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a hig...

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (...

1. Introduction In spite of intensive efforts, still some serious items to be solved remain for high-k gate stack. By narrowing down the items, gate electrode has become one of the most problematic issues due to unavoidable Fermi level pinning [1]. In this talk, after a brief benchmarking of high-k gate stack technology, we lay particular stress on the impact on the electrical characteristics c...