High leakage currents and short channel effects become significant enough to be the major concerns for circuit designers as semiconductor devices are miniaturized. Tunnel field effect transistor(TFET) show good scalability and have very low leakage current .These transistors have very low leakage current, good sub-threshold swing, improved short channel characteristics and lesser temperature se...

The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthr...

In this paper we describe the tunneling junction model effect on silicon nanowire gate-allaround field effect transistor using CMOS 45 nm technology. Tunneling effects provides better subthreshold slope, excellent drain induced barrier lowering and superior ION-IOFF ratio.This paper demonstrates the gate controlled tunneling at source of Gate-all-around field effect transistor. Low leakage curr...

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of previous methods. We describe which figures of merit, including the logical effort, affect the design quality of a cell transistor network. Further, ...

The design of VLSI systems with less power dissipation has become an area of intense research interest. The development for the design of such a low power systems undoubtedly requires the efficient designing methodology. Reversible Logics are one of the alternatives for removing the power dissipation problem in the VLSI systems at logical level implementation. In this regard, at the physical or...

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta2O5 gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-...

Multi-terminal artificial synaptic devices are promising for building neural morphological networks and manufacturing chips. In this study, planar multi-gate InOx-based transistor was demonstrated by using solution-processed AlOx as an electric double layer (EDL) dielectric with mobile hydrogen protons. The excitatory postsynaptic current (EPSC) successfully controlled adjusting amplitude, dura...

Articles you may be interested in Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors Appl. Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors Appl. Effects of gate bias on hot-carrier reliability in drain extended metal-oxide-semiconductor transistors Appl. D...

A two-dimensional numerical analysis is presented to investigate the field effect transistor characteristics, the influence of the geometry of the component like distance between the gate and drain, or between gate and source. All simulations revealed the existence of a high electric field region near the gate contact, who create a depopulated zone around the gate, but the preceding studies hav...

There are two types of field-effect transistors, the Junction Field-Effect Transistor (JFET) and the “Metal-Oxide Semiconductor” Field-Effect Transistor (MOSFET), or Insulated-Gate Field-Effect Transistor (IGFET). The principles on which these devices operate (current controlled by an electric field) are very similar — the primary difference being in the methods by which the control element is ...