The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold logic. The designs include 8 to 64-input AND, 4-bit carry generate, and the carry-out of a (7,3) parallel (population) counter. The circuits are designed using both domino gates and the recently proposed CMOS Charge Rec...

Data with an array structure are common in statistics, and the design or regression matrix for analysis of such data can often be written as a Kronecker product. Factorial designs, contingency tables and smoothing of data on multidimensional grids are three such general classes of data and models. In such a setting, we develop an arithmetic of arrays which allows us to define the expectation of...

A new homogeneous computer architecture developed by FPS combines two fundamental techniques for high-speed computing: parallelism based on the binary n-cube interconnect, and pipelined vector arithmetic. The design makes extensive use of VLSI technology, resulting in a processing node that can be economically replicated. Processor nodes incorporate high-speed communications and control, vector...

This paper describe a system-level approach to improve the area and delay of datapath designs that perform polynomial computations over , which are used in many applications such as computer graphics and digital signal processing domains. This approach optimizes the implementation of multivariate polynomial systems in terms of the number of arithmetic operations by performing optimization on a ...

− This paper describes an analogue processing element (APE) suitable for high-density image sensor/processor array integrated circuits. The design tradeoffs between area, power consumption, speed and accuracy are discussed and the architecture of the APE is presented. The design follows a switched-current “analogue microprocessor” approach while the implementation of arithmetic operations is si...

Current processors typically embeds many cores running at high speed. We may then ask ourselves whether software parallelism is practical for low level arithmetic operations. In this paper we generalize the bipartite modular multiplication method of Kaihara and Takagi. We present a multipartite multiplication. We carefully analyze its asymptotic complexity and measure its practical efficiency a...

This paper presents an implementation of VLSI architecture for Dual Field Residue Arithmetic modular multiplier with less delay based on finite field arithmetic to support all public key cryptographic applications. A new method for incorporating Residue Number System (RNS) and Polynomial Residue Number system (PRNS) in modular multiplication is derived and then implemented VLSI Architecture for...

We discuss floating-point filters as a means of restricting the precision needed for arithmetic operations while still computing the exact result. We show that interval techniques can be used to speed up the exact evaluation of geometric predicates and describe an efficient implementation of interval arithmetic that is strongly influenced by the rounding modes of the widely used IEEE 754 standa...

High radix on-line arithmetic provides an effident m e t h ~ fin" pertbrming wlriahte-precision arithmetic. It can be implemented ~n conventional microprocessors using sequences of three operand instructions. This paper presents ~}ftware support fi~r high radix on-line arithmetic. This software includes emulation modules fi~r high radix operations, and a precision analysis pr~gram fiw setting t...

This paper explains the design and implementation of 8-bit ALU (arithmetic and logic unit) using VHDL by using mixed style of modeling in Xilinx ISE 8.1i. The ALU takes two8-bits numbers and performs different principal arithmetic and logic operations like addition, multiplication, logical AND, OR, XOR, XNOR, NOR. The major focus of concern in this ALU is the multiplication operation using radi...