In safety-critical embedded real-time systems the timing behaviour is of highest importance, because applications underlie timing constraints that have to be met. Otherwise the system might fail causing harm to humans, the environment, or the system itself. Therefore, such hard real-time systems have to provide timing guarantees. Since the timing behaviour of the system does not only depend on ...

In this paper we present a straightforward technique for compressing the instruction stream for programs that overcomes some of the limitations of earlier proposals. After code generation, the instruction stream is analysed for frequently used sequences of instructions from within the program’s basic blocks. These patterns of multiple instructions are then mapped into single byte opcodes. This ...

The demand for mobile computer power has exploded in the recent years. Variable length VLIW processors offer the necessary performance at low power. Software optimizations are necessary to further decrease the energy consumption. In this article we present a compiler optimization which reduces the dynamic power dissipation resulting from the switching activities during instruction fetch. Energy...

Binary translation allows to maintain compatibility across different architectures while still executing at native speeds. To this end, the original program is treated as input to a binary translator which analyzes the program and generates equivalent code for the current base architecture. Binary translation can either occur as a separate step prior to program execution, also referred to as 's...

It has been claimed that the execution time of a program can often be predicted more accurately on an uncached system than on a system with cache memory 5, 20]. Thus, caches are often disabled for critical real-time tasks to ensure the predictability required for scheduling analysis. This work shows that instruction caching can be exploited to gain execution speed without sacriicing predictabil...

This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the performance overheads of prior policies. The proposed policy reduces leakage energy by more than 92% with only less than 0.3% performance overhead on average, whereas prior policies were either prone to severe performance ov...

Instruction cache performance is important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate and the instruction working set size during execution. This means that the performance of an executable can be improved significantly by applying a code-placement algorithm that minimizes instruction cache confl...

This paper provides new insights on how to integrate power-saving techniques by using queue occupancies to dynamically match the power-saving modes of various pipeline stages with the current instruction throughput. (This paper focuses on fetch, decode, integer execution, and data cache.) Architects have proposed many runtime power-saving techniques, most of which reduce power dissipation in a ...

For this study, we analyze the dynamic instruction streams of the SPEC2000 integer benchmarks to find frequently occurring units of computation, or idioms. An idiom, in the broadest sense, is an interdependent piece of a computation dataflow. For example, a load-add-store idiom performs an increment operation through a set of three interdependent instructions. Using a heuristic technique that p...

Instruction cache misses stall the fetch stage of the processor pipeline and hence affect instruction supply to the processor. Instruction prefetching has been proposed as a mechanism to reduce instruction cache (I-cache) misses. However, a prefetch is effective only if accurate and initiated sufficiently early to cover the miss penalty. This paper presents a new hardware-based instruction pref...