A gate that offers different delays for different input-output paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper,...

Despite the simplicity of the hexagonal graphene structure formed by carbon atoms, the electronic behavior shows fascinating properties, giving high expectation for the possible applications of graphene in the field. The Graphene Nano-Ribbon Field Effect Transistor (GNRFET) is an emerging technology that received much attention in recent years. In this paper, we investigate the device performan...

Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ productivity. In this paper, we present a practical method to perform gate sizing, taking also into account the contribution of fixed wiring loads. Closed-form bounds are derived and a simple recursive procedure is develope...

This work explores homo- and heterojunction tunnel field-effect transistor (TFET)-based NAND NOR logic circuits using 30 nm technology compares their performance in terms of power consumption propagation delay. By implementing homojunction TFET-based circuits, it has been observed that consumes less than the gate since current drawn by PTFET pull-up network is higher. The delay lower due to its...

A hetero gate dielectric low band gap material DG Tunnel FET is presented here. The investigated device is almost free from short channel effects like DIBL and t V rolloff. Simulation of the device characteristics shows significant improvement over conventional double gate TFET when compared interms of on current, ambipolar current, roll-off, miller capacitance and, device delay time. Simulatio...

Repeated modular additions and overflow detection are possible in redundant hybrid number systems (RHNS). In this paper a circuit is proposed that implements the overflow-detecting procedure in such systems and allows a mean addition time of about 10.5 gate delays for numbers having a magnitude order normally distributed in the range [−233, 233 − 1], versus a 14 gate delay required by 32-bit CL...

This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. Since the delay under this mode...

Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost,...

We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when t...

In order for dynamic circuits to operate correctly, their inputs must be mono-tonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is...