—This study undertakes the theoretical design, CAD modeling, realization, and performance analysis of a microwave low-noise amplifier (LNA) which has been accurately developed for operation at 3.0 GHz (S-band). The objective of this research is to thoroughly analyze and develop a reliable microstrip LNA intended for a potential employment in wireless communication systems, and satellite applica...

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency facto...

This study entailed the design of a K-band low noise amplifier (LNA) by using 65-nm bulk CMOS process. In designed amplifier, large transistor was used to reduce size lossy gate series inductor, resulting in and high gain. addition, source generation shunt inductors were at input stage enable simultaneous matching. The LNA had 0.67×0.39 mm2 including RF DC pads. A peak gain 19.5 dB minimum figu...

The effects of packaging on the performance of inductively degenerated common-emitter low-noise amplifiers (LNAs) are examined and the equations describing the input impedance, transconductance, voltage gain, and noise figure of the packaged amplifier are derived. From the equations, several guidelines for the LNA design are obtained and a systematic approach for the LNA design can be derived. ...

A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise ...

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of...

Abstract A differential Low-noise Amplifier (DLNA) using 0.13 μm CMOS technology is presented. The amplifier is optimized for Bluetooth Receiver applications operating in the 2.4 2.5 GHz band. The inductive degeneration topology used in the DLNA provides low noise, high gain and a large IIP3. The differential LNA was added a cascade output stage to the Single-ended source degenerated stage. Sim...

in this paper a wideband single stage pseudomorphic high electron mobility transistor (PHMET) amplifier has been designed at 5.8 GHz, the input and output matching circuits have a pi form.Noise cancelling principle and sensitivity analysis are performed .Simulation results have been compared with their correspondence in [10] give 2.71 dB improvement in amplifier gain at the same noise figure (N...

This paper describes a 1.9 GHz, 25 mW , 0.25 μm CMOS Low Noise Amplifier (LNA), intended for use in a DECT (Digital Enhanced Cordless Communications) Receiver. The LNA has been simulated with Cadence Spectre and the results show that it provides a gain of more than 15 dB, for a noise figure of 2dB, and an input referred IP3 of −5dBm. We present the LNA architecture and the circuit analysis alon...

A VHF (30MHz-300MHz) band digitally programmable low noise amplifier (LNA) has been implemented with a 0.25um standard CMOS process for VHF CMMB mobile TV tuners. Utilizing a T-match input network, input matching of more than a decade bandwidth is achieved across all gain settings. Adopting the multiple gated technique, gain flatness enhancement and capacitor reuse etc., the proposed LNA demons...