This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-i...

A power efficient gain adjustment technique is described to realize programmable gain current mirror. The dissipation power changes over the wide gain range of structure are almost negligible. This property is in fact very interesting from power management perspective, especially in analog designs. The simple structure and constant frequency bandwidth are other ever-interesting merits of propos...

In this paper, a method of low power analog testing is proposed. In spite of having Oscillation Based Built in Self-Test methodology (OBIST), a look up table based (LUT) low power testing approach has been proposed to find out the faulty circuit and also to sort out the particular fault location in the circuit. In this paper an operational amplifier, which is the basic building block in the ana...

A distance bounding system guarantees an upper bound on the physical distance between a verifier and a prover. However, in contrast to a conventional wireless communication system, distance bounding systems introduce tight requirements on the processing delay at the prover and require high distance measurement precision making their practical realization challenging. Prior proposals of distance...

The demand for portable electronic devices that offer greater functionality and performance at lower costs and smaller sizes has increased rapidly. This market trend is driving the need for efficient System-on-Chip (SoC) designs, where the power arises as the one of the biggest problems. The microprocessor design has traditionally focused on dynamic power (active power) consumption as the limit...

The design of Low Power Systems-on-Chips (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description with low-level considerations due to technology defaults and variations and increasing system and circuit complexity. This paper describes the major low-level issues, such as dynamic and static power consumption, temperature, techno...

In this paper, we present on-going work on the design and implementation of FFT processors with low power consumption.

This paper presents a new nonv design that incorporates low-voltag PMOS Flash transistors. The de global store, restore and erase o negligible penalty on regular SRA Store/erase operations also do not c power even considering charge Circuit simulations based on exp characteristics demonstrate that 10 operation at ± 6 V is sufficien restoration of the stored bit even und process variation.

Power has become an important aspect in the design of general purpose processors. This thesis explores how design tradeoffs affect the power and performance of the processor. Scaling the technology is an attractive way to improve the energy efficiency of the processor. In a scaled technology a processor would dissipate less power for the same performance or higher performance for the same power...

Low-power design has gained much attention recently, especially for computing on batterypowered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we propose two approaches to reduce BTB accesses. The first approach expects the distance of every two d...