In this paper, a new cache protocol for ring based shared memory multiprocessors is discussed and analyzed. The proposed protocol uses multicasting of rings to reduce the message traversal length. The simulation results show that the proposed protocol with a bidirectional ring improved the system performance by 8% to 30% as compared to Barroso’s protocol using a unidirectional ring. Assuming th...

It is well-known that the Dolev-Yao adversary is a powerful adversary. Besides acting as the network, intercepting, decomposing, composing and sending messages, he can remember as much information as he needs. That is, his memory is unbounded. We recently proposed a weaker Dolev-Yao like adversary, which also acts as the network, but whose memory is bounded. We showed that this Bounded Memory D...

BACKGROUND The temporal lobe in conjunction with the hippocampus is responsible for memory processing. The gamma wave is involved with this process. To develop a human brain protocol, a better understanding of the relationship between gamma and long-term memory is vital. OBJECTIVE A more comprehensive understanding of the human brain and specific analogue waves it uses will support the develo...

To interconnect high speed networks with data rates of 100ּ Mbit/s and more high performance internetworking units are required. Due to the protocol processing bottleneck in communication nodes being the most significant limiting factor of high speed networks, solutions for efficient implementations have to be developed. One approach is based on the use of parallelism for protocol processing. Th...

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for embedded systems are known to read and write data following memory access patterns. Memory access patterns can be used to optimize cache consistency by prefetching data and reducing the number of memory ...

This paper presents a modeling approach based on deterministic and stochastic Petri nets (DSPN's) for analyzing memory consistency protocols for multiprocessors with Distributed Shared Memory (DSM). DSPN's are a numerically solvable modeling formalism with a graphical representation. The modeling approach addresses in particular the performance degradation due to the amount of message exchange,...

Jackal is a fine-grained distributed shared memory implementation of the Java programming language. It aims to implement Java’s memory model and allows multithreaded Java programs to run unmodified on a distributed memory system. It employs a multiple-writer cache coherence protocol. In this paper, we report on our analysis of this protocol. We present its formal specification in μCRL, and disc...

Jackal is a fine-grained distributed shared memory implementation of the Java pro-gramming language. It aims to implement Java’s memory model and allows mul-tithreaded Java programs to run unmodified on a distributed memory system. Itemploys a multiple-writer cache coherence protocol. In this paper, we report onour analysis of this protocol. We present its formal specification i...

A new memory coherence protocol, Tardis, is proposed. Tardis uses timestamp counters representing logical time as well as physical time to order memory operations and enforce sequential consistency in any type of shared memory system. Tardis is unique in that as compared to the widely-adopted directory coherence protocol, and its variants, it completely avoids multicasting and only requires O(l...

The default messaging model for the OpenFabrics “Verbs” API is to consume receive buffers in order—regardless of the actual incoming message size—leading to inefficient registered memory usage. For example, many small messages can consume large amounts of registered memory. This paper introduces a new transport protocol in Open MPI implemented using the existing OpenFabrics Verbs API that exhib...