In order to address the challenges of future integrated circuit design, both logic synthesis and physical design will need to be tightly integrated. This includes integrating the circuit structure information produced by logic synthesis with the placement stage of physical design. The first step is to determine the effects of partitioning decisions on placement performance. This paper describes...

An integrated circuit design facility has been established at APL to help tap the vast potential of very large scale integrated circuits for space applications. A custom N-channel metal-oxide semiconductor chip containing 7000 transistors has been successfully fabricated by a silicon foundry using the design database produced by the APL facility. This project is a tangible step toward creating ...

This paper will review the typical gate drive requirements for the latest generation of high power IGBT modules and present simplified implementations of the required circuits using newly developed hybrid integrated circuit (HIC) building blocks. A newly developed circuit that provides short circuit protection without desaturation detection will also be presented.

Amid the blizzard of design-automation technologies, the analytical MOSFET models (and their associated model parameter sets) receive scant attention from the design community. However, these models and parameter sets are fundamental to the design process, since they represent the critical "communication link" between a design group and its wafer foundry. In particular, analog integrated circui...

Asynchronous design has been considered to avoid problems like high clock frequency generation and distribution, as well as high static power consumption in GaAs digital circuits. This paper discusses the real advantages of implementing such circuits with respect to feasibility, speed performance, power dissipation and ease of design migration from CMOS to GaAs while taking into account several...

This paper describes a new approach which allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. As an application ...

The complexity of Application Specific Integrated Circuits (ASICs) is continuously increasing. Consequently chip-design becomes more and more challenging. To handle this complexity for a fast ASIC development, the existing design process has to become more efficient. To achieve this, we used an approach based on a multi-agent simulation. A mutli-agent system is an intuitive way to represent a t...

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Hardware Trojans are an increasingly significant threat to the integrated circuit (IC) industry in both commercial and military fields due to the progress of globalization and the rapidly improving IC manufacturing technology in various countries. Because of global economic pressures, the development and fabrication of advanced ICs are often outsourced offshore in order to reduce cost. As a res...