An effort is pursued by several European National Measurement Institutes to lower the uncertainties in calibration of UHV measuring systems for lighting impulse. To this end, several reference dividers are investigated as regards their accuracy both for amplitude and for time parameters. At SP RISE Research Institutes of Sweden, a 500 kV resistive reference divider has been in use since 2000. A...

We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling ...

This paper presents a monolithically integrated broadband lumped-element Wilkinson power divider centered at 20 GHz, which was designed and fabricated to uniformly distribute power to arrays of Josephson junctions (JJs) for superconducting voltage standards. This solution achieves a fourfold decrease in chip area, and a twofold increase in bandwidth (BW) when compared to the previous narrowband...

Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristi...

A digital integrated circuit to realize multi-chip phase synchronization of fractional-N PLL with local oscillator divider is designed. An offset fractional frequency ratio added in difference calculation, which effectively avoids the large calculation error under some special ratios. Different from traditional one-time synchronization, a method tracking mode proposed, can further reduce error....

In this paper design of an improved high speed efficient fuzzy logic controller in switched-cap technique is proposed. The controller takes advantage of an improved fuzzifier with less power consumption compared to what previously has been proposed, a high speed minimum circuit (MIN) and a new structure for high speed voltage mode divider. Pipeline structure, high speed, low power supply and vo...

The objective of this paper is to implement a two-phase, interleaved, bidirectional DC/DC converter topology with an improved voltage conversion ratio for electric vehicle (EV) and DC-microgrid systems. In this study, a two-phase interleaved charge-pump topology is introduced to achieve a high voltage conversion ratio with very simple control circuits. In discharge mode, the circuit topology ac...

An easier force single-stage clock multiband adaptable divider with joining together P&s counter is displayed. Changed manifestation of augmented accurate single-stage clock (E-TSPC) based gap by-2/3 counter was planned utilizing pass transistor rationale, which requires stand out transistor to execute both the numbering rationale and the mode determination control. This technique has been inve...