The decision to use a commercial power MOSFET in a harsh radioactive environment[1], such as outer space, is subordinated to the capacity of the device to tolerate single event effects (SEE)[2] caused by single ionising particles. An incident ion may trigger charge generating mechanisms in the active volumes of the device that may give rise to a simple momentary malfunction or to a destructive ...

A new smart interface based on a first-order chargebalanced SC-oscillator is presented for capacitive sensors, which are shunted by a parasitic conductance. In the novel interface, the effect of shunting conductance is reduced by using the charge/discharge method. The effect of the stray capacitances is eliminated by using the two-port measurement. Moreover, all multiplicative and additive erro...

Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can det...

One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circui...

─An on chip low drop out voltage regulator that employs elegant compensation scheme is presented in this paper. The novelty in this design is that the device parasitic capacitances are exploited for compensation at different loads. The proposed LDO is designed to provide a constant voltage of 1.2V and is implemented in UMC 180 nano meter CMOS technology. The voltage regulator presented improves...

A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances between the sensor and the interface circ...

In this paper we present the design and analysis of a distributed regenerative frequency divider (DRFD) based on a novel distributed single-balanced mixer. Artificial transmission lines are incorporated in the distributed single balanced mixer to absorb the parasitic capacitances. The circuit is realized in a 0.18 μm standard CMOS process. It shows a division by two for an input frequency of 40...

One of the topologies that can work at high Power and high Quality simultaneously is the DCI-NPC topology. This new topology has new parts and presents new voltage and distortion errors. One of these new elements are the MOSFET parasitic Diodes. These Parasitic-Diodes presents a Recovery Reverse Time (trr) and its distorting effects generates signal and quality losses, and EMI problems. These p...

Abstract—A convenient method for canceling the parasitic winding capacitance of integrated electromagnetic interference (EMI) filter is proposed. Based on the concept of split ground structure, mutual inductances and structural capacitances can be appropriately utilized to expand the effective frequency range in common mode (CM) noise suppression. Compared with the former approaches, it require...