We present a new sequential normal basis multiplier over GF (2). The gate complexity of our multiplier is significantly reduced from that of Agnew et al. and is comparable to that of Reyhani-Masoleh and Hasan, which is the lowest complexity normal basis multiplier of the same kinds. On the other hand, the critical path delay of our multiplier is same to that of Agnew et al. Therefore it is supp...

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Quadruple, double, and single precision floating point multipliers are implemented using conventional, Canonical Signed Digit (CSD), Vedic, and radix-4 Booth multiplier methods using Verilog language and ...

In this paper VHDL implementation of complex number multiplier using ancient Vedic mathematics and conventional modified Booth algorithm is presented and compared. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplicatio...