The authors compare the perJbrmances of five dynamic loadbalancing strategies. The simulator they ’ue developed lets them measure these performances across a range of network topologies, including a 20 mesh, a 4 0 hypercube, a linear array, and a composite Fibonacci cube. multiprocessor network without load balancing processes processor-generated tasks locally with little or no sharing of compu...

The most determining factors of the performance of a uniprocessor system are its architecture and the technology in which it is implemented. But when a number of such processors are interconnected to form a multiprocessor system, the performance of the whole system is significantly influenced by the nature in which the processors transfer data between each other; e.g. the technology, topology, ...

Recent advances in the development of optical technologies suggest the possible emergence of optical interconnects within distributed shared memory (DSM) multiprocessors. The performance of these DSM architectures must be evaluated under varying values of DSM parameters. In this paper, we develop a Support Vector Regression (SVR) model for predicting the performance measures (i.e. average netwo...

Feature No single method for mitigating the performance problems of centralized and distributed run queues is entirely successful. A hierarchical run queue succeeds by borrowing the best features of both. P erformance of parallel processing systems, especially large systems, is sensitive to various types of overhead and contention. Performance consequences may be serious when contention occurs ...

High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor systemon-chip (MPSOC). The MPSOC a...

A cycle structure is a fundamental network for multiprocessor systems and suitable for developing simple algorithms with low communication cost. Many efficient algorithms were designed with respect to cycles for solving a variety of algebraic problems, graph problems, and some parallel applications, such as those in image and signal processing [2, 16]. To carry out a cycle-structure algorithm o...

Interconnection networks, such as, shared bus and multistage interconnection networks (MINs) are very suitable for the design of shared memory multiprocessors. The existing analytical models of these networks are based on unrealistic synthetic workload for simplicity of the analyses. Also, they consider the networks in isolation without incorporating other architectural details of a multiproces...

Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. This paper summarizes one such multiprocessor architecture called the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus). It also presents enhancements to the network interface and the cache and directory controllers which support cache block...