Network-on-chip (NoC) is an evolving design technology used for growing a packet switched communication infrastructure which contain hundreds of intellectual property (IP) cell in single mutli-processor system on chip (MPSoC). Network interface (NI) is one of the building block which make intellectual property macrocell to be associated to on-chip communication backbone. This work propose the d...

Packet-switched networks-on-chip (NOC) have been advocated as the solution to the challenge of organizing efficient and reliable communication structures among the components of a system-onchip (SOC). A critical issue in designing a NOC is to determine its topology given the set of point-to-point communication requirements among these components. We present a novel approach to on-chip communica...

Graphene-based nanosensors are used in many applications to monitor and survey physical or chemical phenomena. The use of Graphene improves the mechanical, electrochemical, optical, magnetic properties due its such as properties. But there some characteristics measurements that must be taken manufacture sensors. In this work, a Neural Network (NN) has been proposed can predict values UV (ultrav...

Network-on-Chip (NoC) architecture is emerging as a practical interconnection architecture for future systems-on-chip products. In this paper, an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links is proposed. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally exp...

A main challenge for Network-on-Chip (NoC) design is to select a network architecture that suits a particular application. NNSE enables to analyze the performance impact of NoC configuration parameters. It allows one to (1) configure a network with respect to topology, flow control and routing algorithm etc.; (2) configure various regular and application specific traffic patterns; (3) evaluate ...

The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the a...

Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC) architecture is a promising SoC design solution, offering high computational power with lots of flexibilities. However, finding the optimal MPSoC architecture configuration remains an enormous challenge due to its high structural complexity and functional diversity. In this paper, we introduce a Transaction level NoC SIMulator (...

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause...

The communication problem is a challenge issue for Integrated Circuits (ICs), which usually becomes a bottleneck for performance improvement. Three-dimensional integration (3D), as well as network-on-chip (NoC), are two recent design approaches that promise to alleviate the consequences of interconnection degradation. This paper introduces a new methodology for powerefficient application mappin...

Network-on-Chips (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. On-chip network resources can be dynamically configured to improve energy efficiency performance NoC. However, large complex design space in heterogeneous NoC architectures becomes difficult explore within a reasonable time optimal trade-offs performan...