Whirlpool hash function should be capable of processing the input data streams at high speeds. We propose a fully synchronous parallel pipelined architecture with ten stages of pipelining between rounds, and internal pipelining within each round stage. The proposed architecture can tremendously improve the performance of Whirlpool hash function. Our final implementation can encrypt continuous b...

We present conditions under which we can modify the slack of a channel in a distributed computation without changing its behav ior These results can be used to modify the degree of pipelining in an asynchronous system The generality of the result shows the wide variety of pipelining alternatives presented to the designer of a concurrent sys tem We give examples of program transformations which ...

This paper presents high speed direct digital frequency synthesizer (DDFS) based on pipelining phase accumulator (PA). The proposed 12-bit PA contains three pipelining stages with 4-bit carry-lookahead adder (CLA) with the carries ripple between these stages. Comparing results between similar phase accumulator designed with ripple carry adder on, Cyclone III FPGA platform reveals that the propo...

Behavioral synthesis involves compiling an Electronic System-Level (ESL) design into its RegisterTransfer Level (RTL) implementation. Loop pipelining is one of the most critical and complex transformations employed in behavioral synthesis. Certifying the loop pipelining algorithm is challenging because there is a huge semantic gap between the input sequential design and the output pipelined imp...

This paper presents the design and implementation of hybrid wave-pipelined 2D DWT using lifting scheme. In this approach different lifting blocks are interconnected using pipelining and the individual blocks are implemented using WavePipelining (WP). For the purpose of comparison, non pipelined scheme as well as the scheme with pipelining within the blocks and between the blocks is implemented....

This paper describes an alternative to modulo scheduling for loops, in which the first step is to divide instructions into stages by solving a series of min-cut problems constructed from the code graph of the unscheduled loop body. Our algorithm is formulated and implemented in terms of the code graphs of our own “declarative assembly language” for CELL SPUs. We have measured an average 20% red...

This paper presents UNRET (unrolling and retiming), a resource-constrained software pipelining approach aimed at finding a loop schedule with maximum throughput and minimum register requirements. UNRET works in two phases. First, a pipelined loop schedule with maximum throughput is found for a given set of resources. To do this, different unrolling degrees are explored in decreasing order of ex...

Supplementary section for Understanding Networked Applications: A First Course, Morgan Kaufmann, 1999. Copyright notice: Permission is granted to copy and distribute this material for educational purposes only, provided that this copyright notice remains attached. Concurrency is a key to achieving high throughput for repetitive tasks. Assigning separate tasks to different hosts, they can execut...