This paper presents a framework of the distributed concurrent multi-port-testing test system (CMPT-TS) for IP routers under development at Sichuan Network Communication Key Laboratory. Having analyzed the actuality of concurrent testing for routers, this paper develops a distributed architecture of CMPT-TS and discusses its functional components in detail. Moreover, a new test definition langua...

The optical layer can restore the disrupted tralfic on a persall basis in the case of IinWrouter failures. Thus, the optical layer can provide different levels of restoration for different classes of service. IINTRODUCTION 8. MOTIVATION There is an emerging consensus that IP-over-WDM networking architecture is the most suited for the transport and protection of the rapidly growing IP traffic. I...

This paper proposes TONAK, an AWGR-based optical switch with distributed control plane. Simulations results for a 128-port switch show high throughput and low average packet latency for offered loads of up to 75%, while achieving an energy efficiency of ≈ 50pJ/bit. Introduction The ever-growing demand for cloud-based services and high-performance computing is posing major challenges to the scal...

There is a sharp decline in the network performance when wireless link fails as data path Wireless Network-on-Chip (WiNoC). To counteract this problem, we propose fault-tolerance mechanism for efficient retransmission of WiNoC. When an error detected transmission process, works to feed back fault information source node real time via signal lines. In node, highest priority assigned backup retra...

Received Dec 1, 2012 Revised Jan 22, 2013 Accepted Feb 6, 2013 New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. ...

With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with quality of service (QoS) guarantees. In this paper, we explore the feasibility of providing QoS in wormhole switched routers, which are otherwise well known for designing high performance interconnects. In particular, we are interested in supporting multimedia video st...

With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with Quality-of-Service (QoS) guarantees. In this paper, we explore the feasibility of providing QoS in wormhole switched routers, which are widely used in designing scalable, high performance cluster interconnects. In particular, we are interested in supporting multimedia ...

Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance of the on-chip interconnection networks. This paper proposes TagNoC, as an on-chip network router architecture with novel hybrid routing approach which reduces latency and power consumption at a fix...