This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based ...

The hardware implementation of error-tolerant adders using the paradigm approximate computing has considerably influenced performance metrics, especially in applications that can compromise accuracy. foundation for processing is inclusion errors design to enhance effectiveness and reduce complexity. This work presents three base novel concept error tolerance digital VLSI design. research extend...

In this paper, average frequency correlation and rootmean-squared (rms) delay spread estimation for wireless communication systems are described. A practical algorithm for averaged channel frequency correlation estimation, which can be used for measuring frequency selectivity, is given. Average rms delay spread of the channel is obtained directly from the channel frequency correlation estimate ...

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) cell is used for R-VDD architecture with improved stability lower consumption. developed to avoid unessential scaling. In this work, cells are implemented analyzed conside...

The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for ...

This paper presents a method to Designing Ripple Carry Adder using CMOS Full-Adders for Energy-Efficient Arithmetic Applications. We present two high-speed and low-power full-adder cells de-signed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced powerdelay product (PDP). We carried out a comparison against other full-adders reported as ha...

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set , , . In this manuscript we h...

Abstract The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of modern generation. Universal Asynchronous Receiver Transmitter (UART) is one most sought-after protocols. This work focuses on implementing and analysing UART for communication. Finite State Machine (FSM) implements baud rate generator, transmitter, receiver modules. Cadence ...

BACKGROUND D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. FINDINGS The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this,...