A dual-modulus (divide-by-16/17) prescaler has been designed using a 0.35μm CMOS technology. It consists of a divide-by-4/5 synchronous divider and a divideby-4 asynchronous divider, all implemented with MOS current mode logic. The operating frequency range is simulated to be from 0.8 to 3.1 GHz including all parasitics. The prescaler including the output buffers driving external 50Ω load draws...

By increasing the impedance of microstrip combine port, a new Gysel power combiner/divider (PCD) with enhanced average power-handling capability (APHC) was proposed. This article shows simulated results traditional PCD and proposed at center frequency 2.4 GHz 10 GHz. For verification, one example operating designed, fabricated, measured. One also fabricated to compare APHC PCD, by means measuri...

It is proposed that the application of defected ground structures (DGS) and electromagnetic bandgap (EBG) reduce the phase velocity, increase effective permittivity of microstrips and reduce the effective the wavelength which eventually lead to the reduction of overall length of Wilkinson power dividers. Furthermore, the adjacent strip lines may approach each other, which cause coupling problem...

A compact quadruplexer with the functions of frequency division, selection, and power splitting/combining is presented in this article. Four tri-mode stub-loaded resonators were adopted to construct multifunctional a third-order filtering response. The four-channel passbands controlled realized independently by using distribution coupling configuration. output structure was designed be symmetri...

A log-domain current-mode true RMS-to-DC converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. The circuit employs floating gate MOS (FG-MOS) transistors operating in weak inversion region. The converter features low power(

Superharmonic injection locking is investigated in a new theoretical approach. Low power frequency dividers are designed using injection locked oscillators with cascode transistors. The Rockwell 0:5 m CMOS process is used to design a 3mW injection locked frequency divider in the 1800MHz frequency range. A 200MHz maximum locking range is achieved in simulations. 2SC3302 TOSHIBA NPN transistors a...

A simple and analytical design methodology for a novel planar four-port structure to implement power divider (PD) or balun with variable power division is proposed in this paper. It consists of two different 3 dB branch-line couplers and one coupled-line phase shifter whose length can be changed to implement variable power division. Different from the previous designs, the power divider and bal...