In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...

background: since organophosphorus pesticides are widely used for industry and insect control in agricultural crops, their fate in the environment is very important. pesticide contamination of surface water has been recog­nized as a major contaminant in world because of their potential toxicity towards human and animals. the objec­tive of this research was to investigate the influence of variou...

Abstract: In this article, a two-node single-processor Markovian tandem queueing system with task splitting and feedback is considered. Each node has an infinite buffer before it and, thus, no blocking is possible in the system. Splitting feature is added to the model considered and it makes it a novel tandem queue. The functional equation developed from the generating function applied to the s...

Many important synchronization problems in distributed computing are impossible to solve (in a fault-tolerant manner) in purely asynchronous systems, where message transmission delays and relative processor speeds are unbounded. It is then natural to seek for the minimal synchrony assumptions that are sufficient to solve a given synchronization problem. A convenient way to describe synchrony as...

In microprocessor architectures featuring on-chip cache the majority of memory read operations are satisfied without external access. There is, however, a significant penalty associated with cache misses which require offchip accesses when the processor is stalled for some or all of the cache line refill time. This paper investigates the magnitude of the penalties associated with different cach...

We present a novel, compile-time method for determining the cache performance of the loop nests in a program. The cache hit-rates are produced by applying the reference string, determined during compilation, to an architecturally parameterized cache simu-lator. We also describe a heuristic that uses this method for compile-time optimization of loop ranges in iteration-space blocking. The result...

FADI is a complete programming environment that serves the reliable execution of distributed application programs. FADI encompasses all aspects of modern fault-tolerant distributed computing. The built-in usertransparent error detection mechanism covers processor node crashes and hardware transient failures. The mechanism also integrates user-assisted error checks into the system failure model....

We present a novel, compile-time method for determining the cache performance of the loop nests in a program. The cache-miss rates are produced by applying the program's reference string of a loop nest, determined during compilation, to an architecturally parameterized cache simulator. The obtained cache-miss rates correlate well with the performance of the loop nests on actual target machines....

The concept of processor sharing introduces a heuristics to prevent long jobs from blocking short jobs in queue. In practice, round-robin has to be used. In the literature, it is generally assumed that newly arrived jobs are put at the end of the queue. However, for highly varying job demands, such an approach may perform poorly. By favoring newly arrived jobs, which are more likely to be short...