Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however, it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLD...

In this paper we are interested in privacy preserving discretionary access control (DAC) for outsourced storage such as increasingly popular cloud storage services. Our main goal is to enable clients, who outsource data items, to delegate permissions (read, write, delete) to other clients such that clients are able to unlinkably and anonymously perform operations on outsourced data items when h...

Leakage power is becoming the dominant power component in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 9T SRAM cell design considering these leakage issues for ultra low power applications is proposed in this paper. The elementary cell structure of proposed adiabatic SRAM ...

A machine of storage, a machine to compute, a machine to envisage, a magical machine of job parallelization all these describing expressions are not enough to picturise the inevitability of a valuable machine – The Computer. The feature of save and retrieve contributed much to the expert working of the system. The volatile and non-volatile levels of storage have been years long-standing foundat...

RRAM (Redundant Random Access Memory) is a RAM with redundant spares included in the chip. Because of the row/column organization of memory cells in RAMs, these spares are organized as rows and columns. Memory cells which are faulty can be repaired by the spare rows, spare columns and their combinations. Because additional cost of incorporating spares and repairing, it is usually advantageous t...

A new emerging memory technology, Phase-change RAM is gaining more and more attention as a complement or replacement of existing DRAM in the main memory subsystem. In order for PRAM to be applied to the main memory, its limitations of write endurance, long read/write latency, high write power consumption need to be overcome on the PRAM chip and the SoC utilizing the PRAM. In this paper, we expl...

When implementing recursive programs on a standard von Neumann random access machine (RAM) it is natural and well known how to use a pushdown store in order to keep track of the recursive procedure calls when the program runs. The more abstract world of program schemes abounds with examples of this pushdown – recursion relation. As a concrete example it is well known how to implement monadic re...

The gap between processor and memory speeds is one of the greatest challenges that current designers face in order to develop more powerful computer systems. In addition, the scalability of the Dynamic Random Access Memory (DRAM) technology is very limited nowadays, leading to consider new memory technologies as candidates for the replacement of conventional DRAM. Phase-Change Memory (PCM) is c...

Size and weight constraints on wearables limit their battery capacity and restrict them from providing rich functionality. The need for durable and secure storage for personal data further compounds this problem as these features incur energy-intensive operations. This paper presents WearDrive, a fast storage system for wearables based on battery-backed RAM and an efficient means to offload ene...

NetApp is a pioneer in the development of innovative intelligent caching technologies to decouple storage performance from the number of disks in the underlying disk array to substantially improve cost. This white paper describes the NetApp® implementation of write caching using NVRAM as a journal, as well as a three-level approach to read caching that includes the system buffer cache, Flash Ca...