This study presents a resource-efficient reconfigurable inference processor for recurrent neural networks (RNN), named AERO. AERO is programmable to perform on RNN models of various types. was designed based the instruction-set architecture specializing in processing primitive vector operations that compose dataflows models. A versatile vector-processing unit (VPU) incorporated every operation ...

The design of computer instruction sets has been mostly considered as being a manual process, due to complications between hardware and software, and the lack of suitable design tools. The manual process limits understanding of the hardware/ software interface and tradeoffs. Motivated by this limitation, the design automation system ASIA (Automatic Synthesis for Instruction-set Architecture) wa...

Represented by application-specific instruction set processors (ASIPs) and array processors, existing cryptographic face challenges in application to mobile terminals with sensitive security requirements. Typically, ASIPs have limited computational efficiency algorithmic adaptability. An processor requires massive circuits perform fully expansive computations for ciphers, such are unaffordable ...

Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power...

Power consumption is emerging as a key factor limiting computational performance in both mobile and tethered systems. Although there has been significant progress in low-power circuit design and low-power CAD and some work in low-power microarchitectures, there has been little work to date at the level of instruction set architecture (ISA) design for low power computing. Modern ISAs such as RIS...

“From independence to dependence”: the head of Chapter IX in M. Lokve’s book [ 181 must be a program of any attempt to build a limit theory extending the classical one for sums of independent random variables. Lo&e himself suggested replacing dependent summands by their independent copies, but this could not bring much success. The next step in complication consists in dividing the sum into alm...

FPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers’ productivity through balancing flexibility and ease of configuration of the underlying fabric. To truly facilitate full application acceleration, it is often necessary to also include a highly efficient processor that integrates and collaborates with the accelerators while mai...

In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing) in...

A stack-based processor where the instruction set acts on data resided on an evaluation stack, has its performance bottleneck due to the limit of access to the stack. Although the stack-based processor has low performance, it is very low cost to implement. This paper proposes a method to improve the performance of a stack-based processor. A number of fast registers are used to “cache” part of t...

Multimedia applications are characterized by an increased number of data transfers and storage operations. Appropriate transformations can be applied at the algorithmic level to improve crucial implementation characteristics. In this paper, the effect of data-reuse transformations on power consumption and performance of multimedia applications, realized on General Purpose (GPP) and Application ...