A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous...

Now a day’s technology enhancement is at a blistering pace. Merely VLSI has a meteoric rise due to the adoption of new techniques. Static CMOS had a limitation of deploying constant power supply. Less power dissipation is an essential attribute for any optimized design. Varying the power supply is the very thing for preventing the power dissipation. An adiabatic logic is a new technique to redu...

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3–7 GHz is designed and fabricated using a 0.18 μm CMOS process. The proposed structure is a common sourcecommon source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3–7 GHz with simultaneous noise and input matching and low power con...

In this paper the challenge of enhancing the gain and reducing the power requirement of amplifiers, preferably used in biomedical applications is addressed by demonstrating that composite cascode stages, operating in subthreshold/weak inversion regions provide a method of designing a ultra high gain (97dB) and low-power (21μW) op amp with 1.5V power supply. The op amp is designed without compen...

This paper describes a high-gain CMOS low-noise amplifier (LNA) for 2.4/5.2-GHz WLAN applications. The cascode LNA uses an inductor at the common-gate transistor to increase its transconductance equivalently, and therefore it enhances the gain effectively with no additional power consumption. The LNA is matched concurrently at the two frequency bands, and the input/output matching networks are ...

Power consumption is the major issue in VLSI design. In this paper an efficient low power first order sigma delta modulator is designed for oversampled ADC using floating gate folded cascode operational amplifier, in 0.35 μm Technology. Floating gate MOSFET have low power Dissipation hence it is an attractive solution in design of data converters, low voltage op -amp with rail-to-rail input and...

This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, crosscoupled cascode connection, and close-loop pole placement. MOS switches are driven by bootstrapping circuits that do not subject t...

In this paper, feed-forward techniques are revised and used for the design of high-frequency Operational Transconductance Amplifiers (OTA). For the same power consumption and similar transistor dimensions the two-path and three-path folded-cascode OTAs present both smaller settling error and faster response as compared with the typical folded-cascode topology. Also, a No-Capacitor FeedForward (...