A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <2...

A new analytical model for high-frequency noise in RF active CMOS mixers such as single-balanced and doublebalanced architectures is presented. The analysis includes the contribution of non-white gate-induced noise at the output as well as the spot noise figure (NF) of the RF CMOS mixer, while accounting for the non-zero correlation between the gateinduced noise and the channel thermal noise. T...

This paper analyses two front-end receiver architectures intended for GSM900 use; (i) A direct-conversion receiver, and (ii) a low-IF receiver using a poly-phase filter. The aim is to determine the circuit performance required for GSM operation and to compare this to current state-of-the-art CMOS performance. The analysis shows that direct-conversion receivers fail to meet specifications when b...

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modelin...

This paper presented a new structure for the CMOS power amplifiers as more effective trend to amplify radio frequency (RF) signals compared polar PA's by using envelope removal and restoration (EER) technique. Polar PA offers high-efficiency RF-modulated linear signal amplification. However, these need high uniformity between amplitude phase of modulated signals. The last translates promptly in...